This invention relates to a frequency synthesizer comprising a reference frequency generator, a frequency control circuit comprising frequency reduction means which includes a cycle cancellation circuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said cancellation circuit from a pulse source, and a compensation signal circuit connected to the frequency control circuit, the output signal of the compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency that would otherwise be caused by each cancelled cycle.
Such frequency synthesizers are known and are either of the "direct" type in which the output frequency is derived directly from the reference frequency or of the "indirect", or phase lock loop, type in which the output frequency is generated by a variable frequency oscillator forming part of a phase lock loop which locks the oscillator to a predetermined rational fraction, which is to be understood as including a multiple, of the reference frequency.
Examples of direct frequency synthesizers are described in U.K. Patent Specification Nos.: 1,545,953 and 2,062,315, and examples of phase lock loop synthesizers are described in U.K. Patent Specification Nos.: 1,447,418 and 2,068,185. In each type, it is known to use a variable modulus divider to provide the major part of the required frequency reduction, but such dividers can only produce spectrally pure frequencies which are exact subharmonics of the frequency which is to be divided. The frequencies other than subharmonics are produced by a cycle cancellation technique in which predetermined cycles of the frequency to be reduced are cancelled. Such a technique is well known and is alternatively referred to as sidestep programming (see, for example, A. F. Evers and D. J. Martin, "Improved forms of digital frequency synthesisers", IEE Colloquium Digest 1972/11, pp. 9/1 to 9/5), pulse blanking, pulse removal, pulse cancellation, and pulse or cycle swallowing. The technique is also described in Mullard Technical Note 142 "Versatile LSI frequency synthesiser" pp. 8, 9.
In the prior art devices, the pulse source derives the cycle-cancelling pulses from the reference frequency or from the variable frequency oscillator, typically by means of at least a programmable rate multiplier which produces a programmable number of output pulses for a fixed number of input pulses. These output pulses have an average frequency which can be any rational fraction of the frequency from which they are derived. Since they are strobed by the input pulses, however, the periods between successive output pulses may vary and these variations (referred to as "jitter") would produce variations in the output frequency unless a compensation signal circuit is provided to reduce the effects of the jitter.
In the frequency synthesizer described in the above-mentioned Patent Specification No. 1,447,418, the frequency reduction is partly effected by a successive addition rate multiplier which, for each input pulse thereto, adds a programmable increment to an accumulated value and gives an output pulse each time the capacity of the accumulator is exceeded, leaving the excess as a residue in the accumulator. The principle of its operation can readily be appreciated by taking a simple example in which the capacity of the accumulator is unity and each input pulse adds 0.7 to the value in the accumulator. Thus, the accumulator overflows and gives an output pulse for the 2nd, 3rd, 5th, 6th, 8th, 9th, and 10th input pulses--i.e. seven output pulses for ten input pulses. In other words, the average pulse repetition rate has been multiplied by 0.7 by the rate multiplier.
Said patent specification No. '418 describes a system in which the residue in the accumulator is converted to analogue form in a digital-to-analogue converter and the resultant analogue signal is used to compensate for any variation in the output of the phase comparator due to jitter. It was appreciated that the residue in the accumulator at any instant is a function of the amount of phase jitter that the resulting cancelled pulse will cause. While being particularly effective, the electronic circuitry used is nevertheless relatively complex.
In at least the great majority of modern frequency synthesizers, a rate multiplier is used to determine the size of the minimum frequency step and the pulse input is derived either from the reference frequency generator or, in the case of phase lock loop type synthesizers, from a voltage controlled oscillator which provides the output frequency. The compensation signal, which effectively predicts any phase jitter, is derived from the circuitry of, or associated with, the rate multiplier, or at least depends upon the "history" of the pulses which cause the cycle cancellation, in order to provide a predictive compensation signal.